F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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3.6.1. Clock Ports

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP supports two clock output ports.

The two clock output ports can each choose one of the six clock options described in Clock Outputs.

tx/rx_clkout

tx/rx_clkout is an output port that is enabled by default. You can select one of the six clock options described in Clock Outputs as the source for this port, by selecting TX/RX Clock Options > Selected tx/rx_clkout clock source on the TX Datapath Options tab.

tx/rx_clkout2

tx/rx_clkout2 is an additional output port that you can enable by turning on the Enable tx/rx_clkout2 port option in the parameter editor. You can select one of the six clock options as the source for this port, by selecting TX/RX Clock Options > Selected tx/rx_clkout clock source on the TX/RX Datapath Options tab.

The difference between tx/rx_clkout2 and tx/rx_clkout is that it can further divide the six clock options by a factor specified in the tx/rx_clkout2 clock div by menu.

Available tx_clkout2 divide-by options are: 1, 2, 4. Available rx_clkout2 divide-by options are: 1, 2.
Note:
  • The tx_clkout and tx_clkout2 clocks are asynchronous (no phase relationship) to each other and to any other clock output from the IP. You must take the required precautions to do any data transfers between the two clocks.
  • The rx_clkout and rx_clkout2 clocks are asynchronous (no phase relationship) to each other and to any other clock output from the IP. You must take the required precautions to do any data transfers between the two clocks.
Figure 79. tx_clkout and tx_clkout2
Figure 80. rx_clkout and rx_clkout2

When you select user clock 1 or user clock 2 as the source clock for tx/rx_clkout or tx/rx_clkout2, ensure that you also enable user clock 1 or user clock 2, as appropriate. If you are using FHT, you can enable user clock 1 or user clock 2 by enabling Enable FHT TX/RX user clk1 or Enable FHT TX/RX user clk2 in TX/RX FHT PMA on the TX/RX Datapath Options tab.

When using FGT, on the TX side you can enable user clock 1 or user clock 2 by enabling TX User Clock Settings > Enable TX user clock.

tx/rx_coreclkin

tx/rx_coreclkin is an input port for clocking the TX/RX core interface FIFO. Refer to Recommended Connection and Source for the recommended connections. The recommended source clock for tx/rx_clkout and tx/rx_clkout2 when connecting to tx/rx_coreclkin is shown in Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source. The recommended port connections details are shown in Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2.