F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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3.11.6.2. Accessing FHT PMA Registers

For FHT PMA registers with offset address less than 0x48000, you must use the following address:
  • For the channel on lane 0: offset address
  • For the channel on lane 1: offset address + 0x8000
  • For the channel on lane 2: offset address + 0x10000
  • For the channel on lane 3: offset address + 0x18000
Note: Lane 0, 1, 2, or 3 are the physical locations where the channel is placed at and corresponds to FHT0, FHT1, FHT2, and FHT3 respectively.

For FHT PMA registers with offset address greater than 0x48000 and smaller than 0xFFFFC, you can directly use the offset address provided in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map.

For FHT PMA registers with offset address 0xFFFFC, you must use the following address:
  • For the channel 0: 0xFFFFC
  • For the channel 1: 0x1FFFFC
  • For the channel 2: 0x2FFFFC
  • For the channel 3: 0x3FFFFC
Note: The channel number 0, 1, 2, 3 are the logical number of the PMA lanes. For example, a design with four PMA lanes, has transceiver signals tx/rx_serial[3:0]. The signal tx/rx_serial[0] is for channel 0, the signal tx/rx_serial[1] is for channel 1, the signal tx/rx_serial[2] is for channel 2, and the signal tx/rx_serial[3] is for channel 3.