F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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2.4.1.2.1. FGT Reference Clock Receiver Analog Front End

A simplified FGT reference clock receiver analog front end is shown in the following figure.
Figure 51. Simplified FGT Reference Clock RX Analog Front End
When FGT clock input is AC-coupled on board, no external termination or DC biasing is needed. If DC-Coupled on board, external biasing is not required unless a signaling standard other than differential 100 ohm termination is required.
Note: The on-chip internal termination resistors are active once the device is powered on, no matter whether the device is configured or not. The on-chip internal termination resistors are inactive if the device is powered-off.