F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
Public

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3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output

As an example, in a design with four PMA lanes, if you place all the four channels in quad 3 as follows:
  • Logical lane 0 is placed in quad 3, lane 3
  • Logical lane 1 is placed in quad 3, lane 2
  • Logical lane 2 is placed in quad 3, lane 1
  • Logical lane 3 is placed in quad 3, lane 0

You can enable rx_cdr_divclk_link0 and set the source to 0, where logical lane 0 is placed in physical quad 3, lane 3. This output port connects to reference clock 9. The following examples describe the steps to use the FGT attribute access method through opcode 0xB1 to configure RX CDR clock output. Refer to FGT Attribute Access Method for more details.

Because the output connects to reference clock 9, you can configure the output through any quad 3 PMA lane RX CDR clock register. For example, you can use the RX CDR clock register of lane 0, lane 1, lane2, or lane 3. In the following examples, are using quad 3, lane 3.

Steps to Disable the RX CDR Clock Output

  1. Assert rx_reset.
  2. Write 0x0A3B1 to address 0x9003C.
    • 0x0: Data field for RX CDR Clock to disable rx_cdr_divclk_link0.

    • 0xA: Option field to request service, no reset and set parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  3. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b1.
  4. Write 0x023B1 to address 0x9003C.
    • 0x0: Data field for RX CDR clock.

    • 0x2: Option field to deassert request service, no reset and set parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  5. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b0.
  6. Deassert rx_reset.

Steps to Enable the RX CDR Clock Output with Source as Physical Lane 3

  1. Assert rx_reset.
  2. Write 0xE000A3B1 to address 0x9003C.
    • 0xE000: Data field for RX CDR clock to enable rx_cdr_divclk_link0 with source as physical lane 3.

    • 0xA: Option field to request service, no reset and set parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  3. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b1.
  4. Write 0xE00023B1 to address 0x9003C.
    • 0xE000: Data field for RX CDR clock.

    • 0x2: Option field to deassert request service, no reset and set parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  5. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b0.
  6. Deassert rx_reset.

Steps to Read the RX CDR Clock Output Status

  1. Assert rx_reset.
  2. Write 0x083B1 to address 0x9003C.
    • 0x0: Data field for RX CDR clock.

    • 0x8: Option field to request service, no reset and get parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  3. Read address 0x90040.
    • Bit[28:25]: Represent rx_cdr_divclk_link0 source lane ID. When the value <= 3, rx_cdr_divclk_link0 is enabled; when the value = 0xF, rx_cdr_divclk_link0 is disabled.
  4. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b1.
  5. Write 0x003B1 to address 0x9003C.
    • 0x0: Data field for RX CDR clock.

    • 0x0: Option field to deassert request service, no reset and get parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  6. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b0.
  7. Deassert rx_reset

Steps to Change the RX CDR Clock Output Source to Physical Lane 1

  1. Assert rx_reset.
  2. Write 0x6000A3B1 to address 0x9003C.
    • 0x6000: Data field for RX CDR clock to enable rx_cdr_divclk_link0 with source as physical lane 1.

    • 0xA: Option field to request service, no reset and set parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  3. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b1.
  4. Write 0x600023B1 to address 0x9003C.
    • 0x6000: Data field for RX CDR clock.

    • 0x2: Option field to deassert request service, no reset and set parameters.

    • 0x3: Lane number field for physical lane 3.

    • 0xB1: Opcode field for RX CDR clock.

  5. Poll address 0x90040 until bit 14 = 1'b0 and bit 15 = 1'b0.
  6. Deassert rx_reset.