F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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Date 1/24/2024
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3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP supports RS-FEC (528, 514), RS (544, 514), RS (272, 258). You can enable this functionality in the parameter editor by selecting the Enable RS-FEC option on the RS-FEC tab under Common Datapath Options.

F-Tile PMA/FEC Direct PHY Intel® FPGA IP is available in 25G FEC as a building block, which means the smallest module for FEC is one 25G. You must ensure that clock and reset signals are shared from the same 100G FEC core where they implement the IP.

When you turn on the Enable RS-FEC option for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP uses the RS-FEC block, even if it uses only one channel in the IP. You can use the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP core to implement different protocols. You can enable RS-FEC and TX/RX options independently. However, the FEC mode must be the same. If Enable RS-FEC if off, all the options below are grayed out.

There are 32-bit CWBIN counters that are implemented in soft IP. The soft logic converts the 8-bit CWBIN 0-3 register in the FEC block of the Hard IP to 32-bit soft logic registers. You can enable the 32-bit CWBIN counters using the parameter settings and they are available for all FEC modes.
Note: For more information on how to access the 32-bit CWBIN registers, refer to PMA and FEC Direct PHY Soft CSR Register Map. For more information on how to access the other FEC registers, please refer to FEC Register Map.

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP supports the following modes:

  • Ethernet Technology Consortium* (ETC) RS (272,258)
  • IEEE 802.3 RS (528,514) (CL 91)
  • IEEE 802.3 RS (528,514) (CL 91) ETC
  • Fibre Channel RS (528, 514)
  • FlexO RS (528, 514)
  • IEEE 802.3 RS (544,514) (CL 134)
  • Custom IEEE 802.3 RS (544, 514) (CL 134) @26.5625Gbps
  • Interlaken RS (544, 514)
  • Fibre Channel RS (544, 514)
  • FlexO RS (544, 514)
Figure 68. RS-FEC Options in Parameter Editor
Table 35.  RS-FEC Parameters
Parameter Values Description
Enable RS-FEC On/Off Enables the RS-FEC module. Default value is Off.
Note: When the Enable RS-FEC option is on, a separate interface is not available for each PMA by use of the Provide separate interface for each PMA option.
RS-FEC Mode
  • Ethernet Technology Consortium (ETC) RS (272,258)
  • IEEE 802.3 RS (528,514) (CL 91)
  • IEEE 802.3 RS (528,514) (CL 91) ETC
  • Fibre Channel RS (528, 514)
  • FlexO RS (528, 514)
  • IEEE 802.3 RS (544,514) (CL 134)
  • Custom IEEE 802.3 RS (544, 514) (CL 134) @26.5625Gbps
  • Interlaken RS (544, 514)
  • Fibre Channel RS (544, 514)
  • FlexO RS (544, 514)
Specifies the RS-FEC mode for various topologies. Default value is IEEE 802.3 RS (528,514) (CL 91).
Include 32bit soft CWBIN counters On/Off Enables soft implementation of the 32-bit CWBIN 0-3 counters. This parameter is available only when RS-FEC is enabled and greyed out when RS-FEC is disabled.
Reconfig clock frequency 100MHz to 250MHz Available only when 32-bit soft CWBIN counters are enabled. The reconfiguration clock frequency that you are using should be provided here.
Enable RS-FEC loopback On/Off Enables loopback for RS-FEC.
Enable RS-FEC Data interleave pattern On/Off FEC lanes are bit-interleaved on each physical lane. When enabled: 64/80 (only for IEEE 802). Default value is Off.