Visible to Intel only — GUID: nbd1614297401943
Ixiasoft
Visible to Intel only — GUID: nbd1614297401943
Ixiasoft
4.2. IP Port List
The following table lists the ports for the IP; all ports are 1-bit wide.
Port Name | Direction | Description |
---|---|---|
FHT | ||
in_refclk_fht_i | Input | FHT reference clock input port. Must be mapped to device reference clock pin. Maximum of 2 (i = 0 to 1) ports of this type. |
out_fht_cmmpll_clk_i | Output | FHT common PLL output port. Must be connected to protocol IPs, connected to FHT building-block. There can be a maximum of 2(i = 0 to 1) ports of this type. |
FGT and System PLL | ||
in_refclk_fgt_i | Input | FGT and system PLL reference clock input port. Must be mapped to device reference clock pin. This reference clock port can be connected to FGT PMA, system PLL or both. There can be a maximum of 10 (i = 0 to 9) ports of this type. |
avmm_clk | Input | Avalon® memory-mapped interface clock. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off. Intel recommends 100 to 250 MHz for this clock. |
avmm_reset | Input | Avalon® memory-mapped interface reset. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off. |
FGT | ||
out_refclk_fgt_i | Output | FGT Refclk output port. Must be connected to protocol IPs, connected to FGT building-block. There can be a maximum of 10 (i = 0 to 9) ports of this type. |
en_refclk_fgt_i | Input |
FGT reference clock status control signal. This port is only available when the corresponding Refclk #i is active at and after device configuration set as Off. There can be a maximum of 10 (i = 0 to 9) ports of this type.
|
disable_refclk_monitor_i | Input |
FGT reference clock monitor control signal. This port is only available when the corresponding Refclk #i is active at and after device configuration set as Off. There can be a maximum of 10 (i = 0 to 9) ports of this type.
|
refclk_fgt_enabled_i | Output |
FGT reference clock status signal. This port is only available when the corresponding Refclk #i is active at and after device configuration is set to Off. There can be a maximum of 10 (i = 0 to 9) ports of this type.
|
in_cdrclk_i | Input | Input port for FGT reference clock configured as CDR output. This must be connected to protocol IP output CDR port. There can be a maximum of 2 (i = 0 to 1) ports of this type. |
out_cdrclk_i | Output | Output port for FGT reference clock configured as CDR output. This must be connected to one of two FGT reference clock pins that can be configured as CDR outputs. You must specify the location assignment in the Intel® Quartus® Prime Pro Edition software qsf settings file for correct functionality. There can be a maximum of 2 (i = 0 to 1) ports of this type. |
out_coreclk_i | Output | FGT reference clock output port for user logic. This port is only available when the corresponding Export Refclk #i for use in user logic is set to On. |
System PLL | ||
out_systempll_clk_i | Output | Output port of system PLL. This must be connected to system PLL clock input of protocol IP. There can be a maximum of 3 (i = 0 to 2) ports of this type. |
out_systempll_synthlock_i | Output | System PLL lock status port which indicates if system PLL is locked to incoming reference clock. There can be a maximum of 3 (i = 0 to 2) ports of this type. You can use this port as a status or debug signal. |
refclock_ready [2:0] | Input |
System PLL reference clock status control signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set as Off.
When system PLL #i is disabled, bit[i] can be any value and does not matter. When system PLL #i is enabled, after the reference clock is available, you must assert bit[i] to notify the system PLL to start locking to the incoming reference clock. |
refclock_status | Output |
System PLL reference clock status signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set to Off. After you assert the refclock_ready signal, the system PLL starts to phase-lock to the reference clock and outputs its status.
|