F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
Public
Document Table of Contents

3.8.4. Reset Signals—Descriptions

Table 82.  Reset Signal Descriptions
Name Width Domain Direction Type Description
tx_reset 1 Asynchronous Input N/A TX reset input for TX PMAs and TX datapath. Must be kept asserted until tx_reset_ack is asserted. Applies to all TX channels in a F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
tx_reset_ack 1 Asynchronous Output N/A TX fully in reset indicator. This signal asserts following tx_reset assertion and stays asserted for as long as tx_reset is asserted. This signal deasserts following tx_reset deassertion and remains deasserted for as long as tx_reset is deasserted.
rx_reset 1 Asynchronous Input N/A RX reset input for RX PMAs and RX datapath. Must be kept asserted until rx_reset_ack is asserted. Applies to all RX channels in a F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
rx_reset_ack 1 Asynchronous Output N/A RX fully in reset indicator. This signal asserts following rx_reset assertion and stays asserted for as long as rx_reset is asserted. This signal deasserts following rx_reset deassertion and remains deasserted for as long as rx_reset is deasserted.
reconfig_pdp_reset 1 Asynchronous Input Datapath Avalon® Memory Mapped Interface Reconfiguration Interface Reset
reconfig_xcvr_reset 1 Asynchronous Input PMA Avalon® Memory Mapped Interface Active-high synchronous reset. Assert this signal to reset the PMA reconfiguration interface.
tx_ready 1 Asynchronous Output N/A Status port to indicate when TX PMAs and TX datapath are reset successfully and ready for data transfer.
rx_ready 1 Asynchronous Output N/A Status port to indicate when RX PMAs and RX datapath resets are completed, the RX CDRs have locked to data and the recovered line data is ready to be delivered to the parallel interface.
tx_am_gen_start 1 Asynchronous Output N/A When using FEC, indicates when to start sending alignment markers. This clears after tx_am_gen_2x_ack is asserted.
tx_am_gen_2x_ack 1 Asynchronous Input N/A When using FEC, you must indicate to the reset sequencer at least 2 alignment markers were sent since tx_am_gen_start is asserted. This signal should be deasserted after tx_am_gen_start is deasserted.