F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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4.5.1. Guidelines for System PLL Reference Clock

For reference clock, Refclk #i (i = 0 to 9) that are being used by system PLL #n (n = 0, 1, 2):
  • When the parameter Refclk #i is active at and after device configuration is set to On, the refclk #i must be active at and after device configuration time, or else, the system PLL does not lock.
  • When the parameter Refclk #i is active at and after device configuration is set to Off, the refclk #i can be active after device configuration time. After the refclk #i is active, you need to assert refclock_ready[n] signal to indicate system PLL #n reference clock is ready. If you assert the refclock_ready[n] signal before the refclk #i becomes active, the system PLL does not lock and you have to reconfigure the device.
  • Once refclk #i is active, it must be stable and present throughout the device operation and must not go down.
All refclk #i that are being used by system PLLs must have the Refclk #i is active at and after device configuration parameter set to the same value. Only the following two cases are supported.
  • All system PLL reference clocks have the Refclk #i is active at and after device configuration parameter set to On.
  • Or all system PLLs reference clocks have the Refclk #i is active at and after device configuration parameter set to Off.

When Refclk #i is active at and after device configuration parameter is set to Off, an internal clock is used to calibrate and configure the FPGA device. Due to the low frequency of the internal clock, the calibration and configuration takes longer to finish. In addition, after the system PLL #n reference clock is ready, you must assert refclock_ready[n]. This flow may not meet the link up requirements for some IP protocols. You must make sure your design application is compatible with this flow. Intel recommends supplying a stable and running system PLL reference clock at device configuration, and enabling the Refclk #i is active at and after device configuration parameter.

For PCIe interfaces that require compliance to PCIe link training specifications, the reference clock to the system PLL must be available and stable before device configuration begins. You must set the Refclk #i is active at and after device configuration parameter in the F-Tile Reference and System PLL Clocks Intel® FPGA IP to On and drive the reference clock from an independent and free running clock source. Alternately, if the reference clock from the PCIe link is guaranteed to be available before device configuration begins, you may use it to drive the system PLL. Once the PCIe link reference clock is alive, it must never go down.