F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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3.3.2. TX Datapath Options

Figure 62. TX FGT PMA Parameters in Parameter Editor
Table 29.  TX FGT Datapath Parameters
Parameter Values Description
TX FGT PMA Parameters
Enable Gray coding On/Off

Enables Gray coding. Applicable to PAM4 encoding only. When Off, TX sends gray code set to 0xB4. When On, TX sends gray code set to 0x6C. Must be Off for normal operation, or when in internal or external loopback mode.

Default value is Off.
Enable precoding On/Off Enables pre-coding. Applicable to PAM4 encoding only. Default value is Off.
PRBS generator mode 24 disable, PRBS7, PRBS9, PRBS10, PRBS13, PRBS15, PRBS23, PRBS28, PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, SSPRQ Enables hard PRBS generator with the PRBS polynomial selection. Default value is disable.
Enable fgt_tx_beacon port On/Off Enables fgt_tx_beacon port for SATA.
Enable Spread Spectrum clocking On/Off Enables spread spectrum clocking for SATA protocol compliance.
TX FGT PLL Parameters
Output frequency N/A Shows the calculated TX FGT PLL output frequency.
VCO frequency N/A Shows the calculated TX FGT PLL VCO output frequency.
Enable TX FGT PLL cascade mode On/Off

Enable cascade mode for Duplex link only. Default value is Off. Refer to FGT PMA Fractional Mode for more detail.

Enable TX FGT PLL fractional mode On/Off

Enables TX FGT PLL’s fractional mode.

Default value is Off. Refer to FGT PMA Fractional Mode for more detail.

TX FGT PLL integer mode reference clock frequency 25 to 380 MHz Selects the reference clock frequency (MHz) for the TX FGT PLL. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA0.
TX FGT PLL fractional mode reference clock frequency 25 to 380 MHz Selects the reference clock frequency (MHz) in fractional mode for the TX FGT PLL. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA0.
TX User Clock Parameters
Enable TX user clock 1 On/Off Enables and disables TX user clock1. If the clock is not used, you can disable this to save power. Default value is On.
Enable TX user clock 2 On/Off Enables and disables TX user clock2. If the clock is not used, you can disable it to save power. Default value is Off.
TX user clock div by 12- 139.5 Divider values for the TX PLL VCO output frequency. Values from 12 to 139.5 are acceptable in 0.5 increments. The same dividers are shared for both TX user clock 1 and 2. Default value is 100.
Figure 63. TX FHT PMA Parameters in Parameter Editor
Table 30.  TX FHT PMA Parameters
Parameter Values Description
TX FHT PMA Parameters
Select FHT loopback mode PARALLEL_LOOPBACK, SERIAL_EXT_LOOPBACK, SERIAL_ANA_LOOPBACK, REVERSE_PARALLEL_LOOPBACK, WRAP_LOOPBACK, DISABLED Enables FHT loopback modes. Default is SERIAL_EXT_LOOPBACK.
Select FHT Lane PLL refclk source 100, 156.25 Selects the FHT Lane PLL refclk source.
  • 100 selects 100 MHz output from the common PLL to lane PLL.
  • 156.25 selects 156.25 MHz output from the common PLL to lane PLL.
Default value is 156.25.
FHT user clk div33_34 select

DIV_33

DIV_34

DIV_66

DIV_68
Selects one of the four DIV clock output for the TX user clock. Refer to Clocking for more details on how to use this output. Default value is DIV_66.
Enable FHT TX pre-encoder On/Off Enables FHT TX pre-encoder. Default value is Off. This setting must match the link partner's RX pre-encoder setting.
Enable FHT PLL pre-divider On/Off Enables FHT PLL pre-divider. Default value is Off. If disabled, pre-divider value is 1 and if enabled pre-divider value is 2. In certain configurations, where disabling this sets the lane PLL to fractional mode, you must enable this to set the lane PLL in integer mode for better performance.
Enable FHT TX user clk1 On/Off Enables the FHT TX user clk1. Default value is Off.
FHT TX user clk1 select DIV3334

DIV40

FHT TX user clk1 select, you can select DIV3334 (one of the four DIV clocks listed in user div33_34) or DIV40 clock. Default value is DIV3334. Refer to Clocking.
Enable FHT TX user clk2 On/Off Enables FHT TX user clk2. Default value is Off.
FHT TX user clk2 select DIV3334

DIV40

FHT TX user clk2 select, you can select DIV3334 or DIV40 clock. Default value is DIV3334. Refer to Clocking.
24

The PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, and SSPRQ PRBS generator mode settings are not currently supported through the IP GUI, although present in the parameter editor. Do not select any of the unsupported PRBS generator mode settings. Specify these settings using registers.