F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
Public
Document Table of Contents
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3.14.1.2. Enabling the PRBS Generator and Verifier

The PRBS Generator and Verifier provides a method to debug and validate your PMA links.

To enable the PRBS Generator and Verifier, follow these steps:

  1. Set car_tx_clk_src_sel (0x60000[2]) to 1’b1.
  2. Set cfg_tx_bus_take_dft (0x45804[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  3. Set cfg_lane_tx_prbs_en (0x42934[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  4. Specify the PRBS generator pattern cfg_lane_tx_prbs_mode (0x42934[4:1]). If using multi-lanes, specify for all lanes.
  5. Set cfg_lane_tx_prbs_init (0x4293C[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  6. Set cfg_dft_rx_prbs_common_en (0x42930[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  7. Specify the PRBS verifier pattern, cfg_dft_rx_prbs_sel (0x42930[4:1]). If using multi-lanes, specify for all lanes.
  8. Set cfg_rx_dft_data_sel (0x42930[6:5]) to 2’b00. If using multi-lanes, set 2’b00 to all lanes.
  9. Set cfg_ber_symb_cnt_limit_lsb (0x428EC[31:0]). If using multi-lanes, set for all lanes.
  10. Set cfg_ber_symb_cnt_limit_msb (0x428F0[31:0]). If using multi-lanes, set for all lanes.
  11. Set cfg_dft_ber_count_en (0x428DC[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  12. Set cfg_dft_ber_count_mode (0x428DC[2:1]) to 2’b10. If using multi-lanes, set 2’b10 to all lanes.