Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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2.3.4. Parameters

The Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP supports customization of the following parameters.

Table 20.  Parameter Settings




Use as partial reconfiguration internal host On|Off

Enables the controller for use as an internal host. Enabling this option auto-instantiates prblock and crcblock WYSIWYG as part of your design. Disable this option to use the controller as an external host. Connect additional interface signals to the dedicated partial reconfiguration pins.

Enable JTAG debug mode On|Off

Enables access to the controller by the Intel® Quartus® Prime Programmer for partial reconfiguration over a JTAG interface.

Enable Avalon® -MM slave interface On|Off Enables the controller's Avalon® memory-mapped agent interface. When this setting is Off, the IP controller enables the conduit interface.
Enable interrupt interface On|Off Enables interrupt assertion for detection of incompatible bitstream, CRC_ERROR, PR_ERROR, or successful partial reconfiguration. Upon interrupt, query PR_CSR[4:2] for status. Write a 1 to PR_CSR[5] to clear the interrupt. Use only together with the Avalon® memory-mapped agent interface.
Enable freeze interface On|Off

Enables the controller's single-bit freeze interface. This interface identifies whether any region in the design is active or frozen for partial reconfiguration operations. Leave this interface off, and use the freeze interface from the Partial Reconfiguration Region Controller IP.

Enable bitstream compatibility check On|Off

Enables bitstream compatibility checks during partial reconfiguration operation from the external host. Bitstream compatibility check automatically enables when you use partial reconfiguration by internal host. Specify the partial reconfiguration bitstream ID value if you enable this option for partial reconfiguration by external host.

PR bitstream ID <32-bit integer>

Specifies a signed, 32-bit integer value of the partial reconfiguration bitstream ID for the external host. This value must match the partial reconfiguration bitstream ID that the Compiler generates for the target partial reconfiguration design. Locate the partial reconfiguration bitstream ID of the target partial reconfiguration design in the Assembler report (.asm.rpt).

Input data width 1|8|16|32

Specifies the size of the controller's data conduit interface in bits. Refer to Error Detection CRC Requirements.

Clock-to-data ratio 1|4|8

Specifies the clock-to-data ratio that corresponds with the partial reconfiguration bitstream data type. Refer to the Valid combinations and CD Ratio for Bitstream Encryption and Compression Table.

Divide error detection frequency by 1..256

Specifies the divide value of the internal clock. This value determines the frequency of the error detection CRC. The divide value must be a power of two. Refer to device documentation to determine the frequency of the internal clock for the device you select. Refer to Error Detection CRC Requirements.

Enable enhanced decompression On|Off

Enable enhanced decompression of partial reconfiguration bitstreams.

Note: You cannot use enhanced decompression together with encryption simultaneously. Enhanced decompression is only available with the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP.
Table 21.  Advanced Settings




Auto-instantiate partial reconfiguration control block On|Off

Automatically includes the partial reconfiguration control block in the controller. When using the controller as an internal host, disable this option to share the partial reconfiguration block with other IP cores. Rather, manually instantiate the partial reconfiguration control block, and connect the relevant signals to the controller.

Auto-instantiate CRC block On|Off Automatically includes the CRC block within the controller. Leave this option enabled unless you plan to use single event upset (SEU) IP in the same PR design. If you disable this option, IP generation exports the crc_error_pin for manual connection to an external CRC block that you manually instantiate. If you disable this option and then subsequently leave the exported crc_error_pin floating, the PR operation is undetermined due to unexpected crc_error_pin.
Generate timing constraints file On|Off

Automatically generates an appropriate Synopsys Design Constraints (.sdc) file to constrain the timing of the controller. Disable this option when providing timing constraints in another file.

Figure 43.  Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP Parameter Editor