Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021
Public

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1.6.7. Resetting the PR Region Registers

Upon partial reconfiguration of a PR region, the status of the PR region registers become indeterminate. Bring the registers in the PR region to a known state by applying a reset sequence for the PR region. This reset ensures that the system behaves to your specifications. Simply reset the control path of the PR region, if the datapath eventually flushes out within a finite number of cycles. Use active-high local reset instead of active-low, wherever applicable. This technique allows you to automatically hold the PR region in reset, by virtue of the boundary port wire LUT.
Supported PR Reset Implementation Guideline
PR Reset Type Active-High Synchronous Reset Active-High Asynchronous Reset Active-Low Synchronous Reset Active-Low Asynchronous Reset

On local signal

Yes Yes Yes Yes
On global signal
  • No ( Intel® Arria® 10)
  • No ( Intel® Cyclone® 10 GX)
  • Yes ( Intel® Stratix® 10)
  • Yes ( Intel® Agilex™ )
Yes
  • No ( Intel® Arria® 10)
  • No ( Intel® Cyclone® 10 GX)
  • Yes ( Intel® Stratix® 10)
  • Yes ( Intel® Agilex™ )
Yes

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