Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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2.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model

The Intel® Quartus® Prime Pro Edition software supports simulating the delivery of a partial reconfiguration bitstream to the PR control block. This simulation allows you to observe the resulting change and the intermediate effect in a reconfigurable partition.

The Intel® Arria® 10 and Intel® Cyclone® 10 GX PR control blocks support PR simulation. Sending a simulation RBF (PR bitstream) allows the PR control block to behave accordingly, to PR simulation success or PR simulation failure. To activate simulation of a specific PR persona in your PR region simulation wrapper, use a PR ID encoded in the simulation RBF, in conjunction with the PR control block. Simulate the PR control block either as standalone, or as part of the simulation file set for the Partial Reconfiguration Controller IP core.

Figure 72. PR Control Block Simulation Model

The PR control block simulation model contains two additional simulation-only ports—sim_state and sim_pr_id. Connect these simulation ports, and the other ports, to the twentynm_prblock_if SystemVerilog interface. This connection allows monitoring of the PR control block using your testbench’s PR control block monitor. The Intel® Quartus® Prime software automatically instantiates the twentynm_prblock_if interface when generating the simulation file set of the Partial Reconfiguration IP core. Obtain a reference to the twentynm_prblock_if that the IP instantiates by using the alt_pr_test_pkg::twentynm_prblock_if_mgr singleton, as shown in the following example:

virtual twentynm_prblock_if prblock_if;

alt_pr_test_pkg::twentynm_prblock_if_mgr cb_mgr;

// Get the PR control block from the prblock manager
cb_mgr = alt_pr_test_pkg::twentynm_prblock_if_mgr::get();
prblock_if = cb_mgr.if_ref;
The code for the twentynm_prblock_if interface is as follows:
interface twentynm_prblock_if(input logic pr_clk, input logic clk);

    logic prrequest;
    logic [31:0] data;
    wire error;
    wire ready;
    wire done;
    logic [31:0] sim_only_state;
    wire [31:0] sim_only_pr_id;

    // All signals are async except data
	clocking cb1 @(posedge pr_clk);
        output data;
endinterface : twentynm_prblock_if
For more information on the twentynm_prblock_if interface, refer to the <installation directory> /eda/sim_lib/ file.
The simulation state of the PR control block simulation model represents the PR_EVENT_TYPE enumeration state of the control block. The twentynm_prblock_test_pkg SystemVerilog package defines these enumerations. These states represent the different allowed states for the control block. The defined control block enumerations are:
package twentynm_prblock_test_pkg;
    typedef enum logic [31:0] {

When the simulation state is PR_IN_PROGRESS, the affected PR region must have its simulation output multiplexes driven to X, by asserting the pr_activate signal. This action simulates the unknown outputs of the PR region during partial reconfiguration. In addition, you must assert the pr_activate signal in the PR simulation model to load all registers in the PR model with the PR activation value.

Once the simulation state reaches PR_COMPLETE_SUCCESS, activate the appropriate PR persona using the appropriate PR region simulation wrapper mux sel signals. You can decode the region, as well as the specific select signal from the sim_only_pr_id signal of the PR control block. This ID corresponds to the encoded ID in the simulation RBF.

Table 63.  Required Sequence of Words in Simulation RBFStep 1 writes zero or more of the following words. All other steps write only 1 word.
1 zero padding blocks 0x00000000
3 PR_ID 32-bit user ID
4 PRDATA_COUNT_0 0x01234567
Note: The PR_ID word is output on the sim_only_pr_id word, starting at PRDATA_COUNT_0. Using a different value for the header or data count results in PR simulation errors.