Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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2.2.2. Parameters

The Partial Reconfiguration Controller Intel® FPGA IP supports customization of the following parameters.

Table 13.   Partial Reconfiguration Controller Intel FPGA IP Parameter Settings




Enable Avalon-ST sink or Avalon-MM slave interface Avalon-ST/Avalon-MM

Enables the controller's Avalon streaming sink or Avalon memory-mapped slave interface.

Input data width <bits>

Specifies the size of the controller's data conduit interface in bits. The IP supports device widths of 32 and 64.

Enable interrupt interface


Enables interrupt assertion for detection of incompatible bitstream, CRC_ERROR, PR_ERROR, or successful partial reconfiguration. Upon interrupt, query PR_CSR[4:2] for status. Write a 1 to PR_CSR[5] to clear the interrupt. Use only together with the Avalon® memory-mapped agent interface.
Enable protocol error   Reads out the error bit from the CSR register.
Figure 38. Parameter Editor