Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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Document Table of Contents Applying Floorplan Constraints Incrementally

PR implementation requires additional constraints that identify the reconfigurable partitions of the design and device. These constraints significantly impact the Compiler's timing closure ability. You can avoid and more easily correct timing closure issues by incrementally implementing each constraint, running the Compiler, then verifying timing closure.
Note: PR designs require a more constrained floorplan, compared to a flat design. The overall density and performance of a PR design may be lower than an equivalent flat design.
The following steps describe incrementally developing the requirements for your PR design:
  1. Implement the base revision using the most complex persona for each PR partition. This initial implementation must include the complete design with all periphery constraints, and top-level .sdc timing constraints. Do not include any Logic Lock region constraints for the PR regions with this implementation.
  2. Create partitions by setting the region Type option to Default in the Design Partitions Window, for all the PR partitions.
  3. Register the boundaries of each partition to ensure adequate timing margin.
  4. Verify successful timing closure using the Timing Analyzer.
  5. Ensure that all the desired signals are driven on global networks. Disable the Auto Global Clock option in the Fitter (Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)), to avoid promoting non-global signals.
  6. Create Logic Lock core-only placement regions for each of the partitions.
  7. Recompile the base revision with the Logic Lock constraints, and then verify timing closure.
  8. Enable the Reserved option for each Logic Lock region to ensure the exclusive placement of the PR partitions within the placement regions. Enabling the Reserved option avoids placing the static region logic in the placement region of the PR partition.
  9. Recompile the base revision with the Reserved constraint, and then verify timing closure.
  10. In the Design Partitions Window, specify the Type for each of the PR partitions as Reconfigurable. This assignment ensures that the Compiler adds wire LUTs for each interface of the PR partition, and performs additional compilation checks for partial reconfiguration.
  11. Recompile the base revision with the Reconfigurable constraint, and then verify timing closure. You can now export the top-level partition for reuse in the PR implementation compilation of the different personas.