2.4.3. Configuring an External Host for Intel® Stratix® 10 or Intel® Agilex™ Designs
The external host must respond appropriately to the handshake signals for successful partial reconfiguration. Co-ordinate system-level partial reconfiguration by ensuring that you prepare the correct PR region for partial reconfiguration. After reconfiguration, return the PR region into operating state.
To configure an external host for Intel® Stratix® 10 or Intel® Agilex™ designs, follow these steps:
- Parameterize and generate the Partial Reconfiguration External Configuration Controller Intel FPGA IP, as Specifying the IP Core Parameters and Options ( Intel Quartus Prime Pro Edition) describes.
- Connect the Partial Reconfiguration External Configuration Controller pr_request, pr_done, and pr_error signals to top-level pins for control and monitor by the external host. You can assign the pin location by clicking Assignments > Pin Planner.
- Click Assignments > Device, and then click the Device & Pin Options button.
- In the Category list, click Configuration.
- For the Configuration scheme, select the scheme that matches with your full device configuration. For example, if your full device configuration uses the AVSTx32 scheme, the PR configuration must use AVSTx32.This option automatically reserves dedicated Avalon® streaming configuration pins for partial reconfiguration during user mode. The pins are exactly same as the Avalon® streaming pins that you use for full device configuration.
The following table describes the PR pins that the external host uses. The PR streaming to Avalon® streaming pins must conform to the Avalon® streaming specification for data transfer with backpressure.
|pr_request||Input||User-assigned port connected to Partial Reconfiguration External Configuration Controller IP. Logic high on this pin indicates that the PR host is requesting partial reconfiguration.|
|pr_done||Output||User-assigned port connected to Partial Reconfiguration External Configuration Controller IP. Logic high on this pin indicates that the partial reconfiguration is complete.|
|pr_error||Output||User-assigned port connected to Partial Reconfiguration External Configuration Controller IP. Logic high on this pin indicates an error in the device during partial reconfiguration.|
|Input||These pins provide connectivity for the external host to transfer the PR bitstream to the SDM. The avstx8 data pins are part of the SDM I/O. avstx16 and avstx32 data pins are from I/O 48 bank 3A.|
|avst_clk||Input||Clocks the Avalon® streaming interfaces. avst_data and avst_valid are synchronous with avst_clk. The avstx8 clk pin is part of the SDM I/O. avstx16 and avstx32 are from I/O 48 bank 3A.|
Logic high on this pin indicates the data in avst_data is valid data. The avstx8 data pins are part of the SDM I/O. avstx16 and avstx32 data pins are from I/O 48 bank 3A.
|avst_ready||Output||Logic high on this pin indicates the SDM is ready to accept data from an external host. This output is part of the SDM I/O.|
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