Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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Document Table of Contents Viewing Row Clock Region Boundaries

You can use the Chip Planner to visualize the row clock region boundaries, and to ensure that no two PR regions share a row clock region.
  1. Right-click a PR partition name in the Design Partitions Window and click Locate Node > Locate in Chip Planner.
    Figure 27. Row Clock Region Boundaries in Chip Planner
  2. In Chip Planner, click the Layers tab and select the Basic layer. The Chip Planner overlays the row clock region boundaries. Adjust the Basic layer settings to display specific items.