Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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1.6.8. Promoting Global Signals in a PR Region

In non-PR designs, the Intel® Quartus® Prime software automatically promotes high fan-out signals onto dedicated global networks. The global promotion occurs in the Plan stage of design compilation.

In PR designs, the Compiler disables global promotion for signals originating within the logic of a PR region. Instantiate the clock control blocks only in the static region, because the clock floorplan and the clock buffers must be a part of the static region of the design. Manually instantiating a clock control block in a PR region, or assigning a signal in a PR region with the GLOBAL_SIGNAL assignment, results in compilation error. To drive a signal originating from the PR region onto a global network:

  1. Expose the signal from the PR region.
  2. Drive the signal onto the global network from the static region.
  3. Drive the signal back into the PR region.

You can drive a maximum of 33 clocks (for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices), or 32 clocks (for Intel® Agilex™ and Intel® Stratix® 10 devices) into any PR region. You cannot share a row clock between two PR regions.

The Compiler allows only certain signals to be global inside a PR region. Use only global signals to route secondary signals into a PR region, as the following table describes:

Table 7.  Supported Signal Types for Driving Clock Networks in a PR Region
Block Type Supported Global Network Signals
RAM, ROM (M20K) Clock, ACLR, Write Enable (WE), Read Enable (RE), SCLR
3 Only Intel® Agilex™ and Intel® Stratix® 10 designs support global SCLR.