Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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Document Table of Contents

1.15. Creating a Partial Reconfiguration Design Revision History

Document Version Intel® Quartus® Prime Version Changes
2021.10.04 21.3
  • Updated PR Bitstream Security Validation topic to refer to Programming File Generator and revise figure.
  • Updated PR File Management topic for new QSF assignment method.
  • Clarified device support and corrected code example in Generating a Merged .pmsf File from Multiple .pmsf Files topic.
  • Revised Version-Compatible Database Flow for PR Designs topic equation and figure.
  • Updated non-inclusive terms with "host" and "agent" for Avalon Memory Mapped interface references throughout.
2021.08.02 21.2
  • Updated Register States and Programming Model diagram.
  • Updated Avoiding PR Programming Errors topic SEU note.
2021.06.21 21.2
  • Updated Version-Compatible Compilation Database Support table.
2021.05.06 21.1
  • Indicated support for Intel® Agilex™ design PR bitstream generation, and removed PR bitstream generation limitation notes.
  • Revised Partial Reconfiguration Design Debugging topic.
  • Revised Debugging PR Designs with the Signal Tap Logic Analyzer topic.
  • Added new Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic topic.
  • Updated Partial Reconfiguration Security topic for latest information.
  • Updated PR Bitstream Security Validation topic license statement and to remove outdated references.
  • Revised PR Authentication topic use cases.
  • Revised PR Authentication topic use cases.
  • Revised PR Bitstream Encryption topic use case and prerequisites.
2020.12.11 20.3
  • Corrected typo in PMSF file definition in "Using PR Bitstream Security Verification"
2020.09.28 20.3
  • Added note about preserving SDC files to "Step 8: Setup PR Implementation Revisions" topic.
  • Added new "Using Parent QDB Files from Different Compiles" topic.
  • Added "PR Design Timing Closure Best Practices" topic.
  • Replaced references to Avalon-MM and Avalon-ST with Avalon® memory-mapped and Avalon® streaming for legal compliance.
2020.08.07 20.2
  • Added screenshot and details about Synthesis report to "Evaluating PR Region Initial Conditions" topic.
  • Added details about Include entity-bound SDC files option requirements to "Step 7: Compile the Base Revision and Export the Static Region" topic.
  • Removed stated support for "PR Bitstream Security Verification" for Intel® Agilex™ devices. This feature is not yet supported for Intel® Agilex™ devices.
  • Added details about Include entity-bound SDC files option requirements to "Generating a Version-Compatible Compilation Database" for PR Designs topic.
  • Added reference to "EDA Netlist Writer and Gate Level-Netlists" section of the Intel® Quartus® Prime Pro Edition User Guide: Third Party Simulation to the "Partial Reconfiguration Design Simulation" section.
2020.06.22 20.2
  • Added PR simulation support for Intel® Agilex™ designs.
2020.05.11 20.1
  • Revised description of PR bitstream compatibility checking steps for Intel® Cyclone® 10 GX and Intel® Arria® 10 devices.
2020.04.13 20.1
  • Updated requirements in "Partial Reconfiguration Bitstream Compatibility Checking" topic.
  • Added note about time borrowing to "Partial Reconfiguration Design Timing Analysis" topic.
  • Added note indicating HPR designs do not support PR security bitstream verification.
2019.11.18 19.3.0
  • Changed title of "Migrating PR Regions to a Later Software Version" to "Exporting a Version-Compatible Compilation Database for a PR Design," generalized examples, and removed INI requirement.
2019.09.30 19.3.0
  • Added compilation support for Intel® Cyclone® 10 GX and Intel® Agilex™ PR designs.
  • Updated IP name from "Partial Reconfiguration Controller Intel Stratix 10 FPGA IP" to "Partial Reconfiguration Controller Intel FPGA IP" to encompass Intel® Agilex™ designs.
  • Updated wording of "Clock Gating" topic for clarity.
  • Added note to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP "Parameters" topic about support for enhanced decompression.
2019.06.10 19.1.0
  • Added details about synthesis of PRESERVE_FANOUT_FREE_NODE to "Partial Reconfiguration Design Guidelines."
2019.04.22 19.1.0
  • Indicated support for POF generation support for Intel Cyclone GX devices.
  • Corrected code example in "PR Migration Flow" topic.
2019.04.01 19.1.0
  • Described migration of the static region of a PR design to a later version of the Intel® Quartus® Prime software.
  • Described new "PR Bitstream Security Validation" feature.
  • Described new location of auto export from output_files to project directory.
2018.12.30 18.1.1
  • Described "Partial Reconfiguration Bitstream Compatibility Check" and PR region limitations.
2018.10.24 18.1.0
  • Added "PR File Management" topic.
  • Updated first guideline in "Partial Reconfiguration Design Guidelines."
2018.09.24 18.1.0
  • Described automated .qdb partition export in "Exporting a Design Partition."
  • Added details about required assignments to "Step 6: Create Revisions for Personas."
  • Removed references to placed snapshot. Only synthesized and final snapshots are supported.
  • Corrected description of Entity Re-binding option in Design Partition Settings table.
  • Added command line instructions for creating a revision.
  • Stated PR compilation flow support for Intel® Cyclone® 10 GX devices.
  • Updated Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP name to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  • Added "Viewing Row Clock Region Boundaries."
  • Added "Planning Clocks and other Global Routing."
2018.07.18 18.0.0
  • Corrected signals in Simulation of PR Persona Switching diagram.
2018.06.18 18.0.0
  • Corrected syntax errors and added note in Running Timing Analysis on Aggregate Revisions.
2018.05.29 18.0.0
  • Added description of "|" that identifies the root partition hierarchy path in Design Partitions Window.
  • Clarified .qsf assignment in Running Timing Analysis on Aggregate Revisions.
2018.05.07 18.0.0
  • Added description of new Partial Reconfiguration External Configuration Controller Intel® Stratix® 10 FPGA IP.
  • Removed descriptions of obsolete synthesis-only revisions and corresponding personas. Replaced with latest simplified flow instructions.
  • Updated names of Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP and Partial Reconfiguration Controller Intel® Stratix® 10 FPGA IP.
  • Added Design Partition Settings topic.
  • Added Evaluating PR Partition Initial Conditions topic.
  • Added Avoiding PR Programming Errors topic.
  • Described qcrypt incompatibility with Enable bitstream compatibility check and workaround.
  • Added as chapter in new Partial Reconfiguration User Guide.
  • Updated command-line syntax in Running Timing Analysis on Aggregate Revisions topic.
  • Removed obsolete HPR flow script information and linked to AN826: Hierarchical Partial Reconfiguration Tutorial for Intel Stratix 10 GX FPGA Development Board
  • Added note about recovery after PR error when using SEU detection in Intel® Stratix® 10 designs.
2017.11.06 17.1.0
  • Added partial reconfiguration support for Intel® Stratix® 10 devices.
  • Added descriptions of Intel® Stratix® 10 Partial Reconfiguration Controller IP, SUPR, HPR, and SDM to terms list.
  • Updated for latest Intel® branding and software user interface.
2017.05.08 17.0.0
  • Added information about Hierarchical Partial Reconfiguration.
  • Added new topic Partial Reconfiguration Simulation and Verification.
  • Added new topic 'Run Timing Analysis on a Design with Multiple PR Partitions'.
  • Updated Freeze Logic for PR Regions.
  • Added new topic Debugging Using Signal Tap Logic Analyzer.
  • Other minor updates.
10.31.2016 16.1.0
  • Initial release.