Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.5.2. Step 2: Create Design Partitions

Create design partitions for each PR region that you want to partially reconfigure. Create any number of independent partitions or PR regions in your design. Create design partitions for partial reconfiguration from the Project Navigator, or the Design Partitions Window.

A design partition is only a logical partitioning of the design, and does not specify a physical area on the device. You associate a partition with a specific area of the FPGA using Logic Lock Region assignments. To avoid partitions obstructing design optimization, group the logic together within the same partition. If your design includes a hierarchical PR flow with parent and child partitions, you can define multiple parent or child partitions in your design, and multiple levels of PR partitions.

When you create a Reconfigurable partition, the Compiler preserves post-synthesis results for the partition and reuses the post-synthesis netlist, if you make no partition changes requiring re-synthesis. Otherwise, the Compiler resynthesizes the partition from source files. The Compiler adds wire LUTs for each interface of a Reconfigurable partition, and performs checks for PR compatibility.

Creating a Design Partition

Follow these steps to create design partitions:

  1. Click Processing > Start > Start Analysis & Elaboration.
  2. In the Project Navigator, right-click an instance in the Hierarchy tab, click Design Partition > Set as Design Partition. A design partition icon appears next to each partition you create.
  3. To view and edit all design partitions in the project, click Assignments > Design Partitions Window.
  4. Specify Reconfigurable as the partition Type for each PR partition. The Reconfigurable type preserves synthesis results, while allowing refit of the partition in the PR flow.
    Figure 7. Design Partitions Window