Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021

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1.13. Avoiding PR Programming Errors

You can use the following guidelines to avoid or resolve common PR programming errors.
Table 9.  PR Programming Guidelines
PR Programming Guideline Description
Device in project must match device on board Confirm the target FPGA device that you specify for the project matches the device on the development kit you target. These two devices must be the same. Click Assignments > Device to view the target device.
Programmer versions must match When using the Intel® Quartus® Prime Programmer for PR programming, confirm that the Programmer version matches the Intel® Quartus® Prime version that you use for compilation. A mismatch between the Programmer and Intel® Quartus® Prime software version can occur if you compile on one machine, and then program on a different machine with a different Intel® Quartus® Prime version. The software version match is especially critical for Intel® Stratix® 10 and Intel® Agilex™ designs because the PR configuration hardware has dependencies inside the Programmer.
Specify a lower JTAG clock frequency Lower the JTAG clock frequency to 6MHz:
  1. In the Programmer window, click Hardware Setup, and then select Intel® FPGA Download Cable II as the programming hardware.
  2. For the Hardware frequency, specify a value from 24000000 (24MHz) to 6000000 (6MHz).
Close timing for all revisions Confirm that each project revision closes timing after design compilation:
  1. In the Compilation Report, expand the Timing Analyzer > Slow 900mV 100C Model folders, and then view the Setup Summary, Hold Summary, Recovery Summary, Removal Summary, and Minimum Pulse Width Summary reports. In each report, verify that there are no timing violations indicated by a negative Slack value in the report.
  2. Repeat step 1 to verify timing closure in the Slow 900mV 0C Model, the Fast 900mV 100C Model, and the Fast 900mV 0C Model. The design closes timing when there are no negative Slack values for any clock in the report.
  3. Repeat steps 1 and 2 for each project revision in the PR design.
Note: If an error occurs during PR operation for an Intel® Stratix® 10 or Intel® Agilex™ design using SEU detection, the PR region is frozen, becomes non-functional, and SEU detection is disabled for all sectors within the PR region and certain sectors adjacent to PR region. To resolve this error and restore SEU detection on affected areas, perform a full chip configuration.