Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 12/12/2022
Document Table of Contents

3.5.2. Timing Preservation

The following techniques can help you preserve timing in designs that include the Signal Tap logic analyzer:

  • Avoid adding critical path signals to the .stp file.
  • Minimize the number of combinational signals you add to the .stp file, and add registers whenever possible.
  • Specify an fMAX constraint for each clock in the design.

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