Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 12/12/2022
Document Table of Contents Add Simulator-Aware Node Finder Settings

The following options are available for searching and adding simulator aware nodes to Signal Tap for the purpose of generating an RTL simulation testbench from Signal Tap data. The default values derive from Signal Tap signal data and are set correctly for most scenarios.
Table 10.  Add Simulator Aware Node Finder Settings (Signal Tap Logic Analyzer)
Name Description
Select Hierarchies Specifies the design hierarchy from which to extract simulator-aware nodes. Select one or more design hierarchies that you want to tap. The clock domains of the hierarchy appear in the Clock Domains list. Only nodes from the hierarchy you specify are added.
Clock Domains Specifies the clock domains to include in the simulator-aware node finder. Turn on only the domains that you want to include.
Search button Starts the search for simulator-aware nodes according to the specifications in this dialog box. Search results appear in the Total nodes to tap list.
Total nodes to tap Displays the results of the simulator-aware node name search, showing all of the names in the hierarchy enabled by default. Turn the node names on to include or off to exclude from the list of nodes added to Signal Tap. Disabling any of the simulator-aware nodes may reduce simulation visibility.
Insert Button Copies the enabled signals in the Total nodes to tap list to the Signal Tap Node list, and the acquisition clock updates according to the simulator-aware signal data.

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