Visible to Intel only — GUID: mwh1410384954353
Ixiasoft
Visible to Intel only — GUID: mwh1410384954353
Ixiasoft
7.2.2. In-System Sources and Probes IP Core Parameters
Port Name | Required? | Direction | Comments |
---|---|---|---|
probe[] | No | Input | The outputs from your design. |
source_clk | No | Input | Source Data is written synchronously to this clock. This input is required if you turn on Source Clock in the Advanced Options box in the parameter editor. |
source_ena | No | Input | Clock enable signal for source_clk. This input is required if specified in the Advanced Options box in the parameter editor. |
source[] | No | Output | Used to drive inputs to user design. |
You can include up to 128 instances of the in-system sources and probes IP core in your design, if your device has available resources. Each instance of the IP core uses a pair of registers per signal for the width of the widest port in the IP core. Additionally, there is some fixed overhead logic to accommodate communication between the IP core instances and the JTAG controller. You can also specify an additional pair of registers per source port for synchronization.
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