Visible to Intel only — GUID: kyz1507138543101
Ixiasoft
Visible to Intel only — GUID: kyz1507138543101
Ixiasoft
3.9.4.1. Signal Tap Debugging with a Core Partition
To perform Signal Tap debugging in a core design partition that you reuse from another project, you identify the signals of interest, and then make those signals visible to a Signal Tap logic analyzer instance. The Intel® Quartus® Prime software supports two methods to make the reused core partition signals visible for Signal Tap monitoring: by creating partition boundary ports, or by Signal Tap HDL instantiation.
Section Content
Partition Boundary Ports Method
Debug a Core Partition through Partition Boundary Ports
Export a Core Partition with Partition Boundary Ports
Signal Tap HDL Instance Method
Export a Core Partition with Signal Tap HDL Instances
Debug a Core Partition Exported with Signal Tap HDL Instances
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