2.8.1. Preserve for Debug Overview
The preserve for debug feature allows you to designate nodes in your design for full debugging visibility. In this context, full visibility means that you can ensure that the node name remains in the post-fit netlist generated by Place and Route, with the same name and functionality the design files define.
After you apply preserve for debug, you can easily access these nodes through the Node Finder filters available in the Intel® Quartus® Prime debugging tools.
Typically, you lose some visibility into the design when you debug using a post-fit netlist. This loss occurs because in the post-fit netlist, the design is already mapped to the device architecture, optimized, and retimed. The Place and Route stage often changes or removes the original signal names. Furthermore, there can be slight changes in the behavior in the post-fit netlist because of inverter push back, or because the visible signal shows only partial behavior due to logic duplication.
Preserve for Debug Use Cases
Preserve for debug is primarily for debugging purposes, and is particularly useful in the Signal Tap debugging flow, as Preserving Signals for Monitoring and Debugging describes.
In addition, use of preserve for debug can also be helpful in any of the available system debugging tools, or within any instrumentation logic that you use in your design.
Preserve for Debug Hardware Implementation
Applying the preserve for debug feature has the following effects on hardware implementation:
- Prevents the Compiler from optimizing the specified node.
- Results in LCELL module instantiation for the specified node, impacting the overall timing on the node path.
Application of preserve for debug is the hardware equivalent of using all of the following HDL pragmas on the specified node:
|HDL Pragma||Compiler Setting||Description|
|preserve||PRESERVE_REGISTER||Prevents the Compiler from optimizing away or retiming a register.|
|keep||HDL only||Prevents the Compiler from minimizing or removing a particular signal net during combinational logic optimization.|
|noprune||HDL only||Prevents the Compiler from removing or optimizing a fan-out free register.|
|dont_merge||HDL only||Prevents the Compiler from merging a register with a duplicate register.|
|dont_replicate||HDL only||Prevents the Compiler from merging a register with a duplicate register.|
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