3.9.4. Debugging Block-Based Designs with Signal Tap
Verifying a block-based design requires planning to ensure visibility of logic inside partitions and communication with the Signal Tap logic analyzer. The preparation steps depend on whether you are reusing a core partition or a root partition.
For information about designing with reusable blocks, refer to the Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design . For step-by-step block-based design debugging instructions, refer to AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board.
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