Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 12/12/2022

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3.2. Signal Tap Debugging Flow

To use the Signal Tap logic analyzer to debug your design, you compile your design that includes one or more Signal Tap instances that you define, configure the target device, and then run the logic analyzer to capture and analyze signal data.

When Should I Add Signal Tap to the Design?

It is best to add the Signal Tap logic analyzer to your design early in the design flow to help prevent later difficulty in fitting the Signal Tap logic into the target device. If you add Signal Tap late in the design cycle, you may have difficulty with fitting if the device is already at 90-95% full. However, you can use the ECO compilation feature to add Signal Tap as soon as you initially create the design, even before adding nodes or running synthesis. This technique allows you to more easily make the ECO connections later if needed. Refer to Using the ECO Compilation Flow in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.

Figure 21.  Signal Tap Debugging Flow

The following steps describe the Signal Tap debugging flow in detail: