ID 683819
Date 12/12/2022
Public

3.9.1.1. Generating a Simulation Testbench from Signal Tap Data

You can use Signal Tap to capture signal data about your running system, and then automatically generate an RTL simulation testbench directly from this capture data for use in your supported simulator.

To generate a simulation testbench from Signal Tap data, follow these steps:

1. Add simulator-aware Signal Tap nodes to the logic analyzer, as Adding Simulator-Aware Signal Tap Nodes describes.
2. Run Signal Tap analysis, as Step 5: Run the Signal Tap Logic Analyzer describes.
Figure 87. Create Simulation Testbench
3. In the Signal Tap window, click File > Create Simulation Testbench. Retain defaults and click OK. The testbench generates in a vendor-specific directory. Refer to Create Simulation Testbench Dialog Box Settings.
4. Source the generated simulator setup script in your supported simulator. For example:
source msim_setup.tcl
5. Use the commands in the setup script to compile and load the testbench into a supported simulator. For example, in the Questa or ModelSim simulators:
ld_debug
Note: Signal Tap uses a Verilog HDL force statement to inject the Signal Tap data into the simulator.
6. Add signals to the waveform and run the simulation in your simulator.
7. View the results of simulation in your simulator.