AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.3.3. Transport Layer

The transport layer in the reference design consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is implemented in the top level HDL file, not in the Qsys project.

The transport layer provides the following services to the application layer (AL) and the link layer:

  • The assembler at the TX path:
    • maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
    • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.
  • The deassembler at the RX path:
    • maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
    • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.

The transport layer has many customization options and you can modify the transport layer HDL code to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the transport layer in the same way.

The software instructions to execute dynamic reconfiguration of the transport layer are described in the User Commands section.

Did you find the information on this page useful?

Characters remaining:

Feedback Message