AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.3.1.3.1. JESD204B IP Core

The JESD204B IP core is configured in duplex (with TX and RX data paths), non-bonded mode with the following parameter configuration:

Table 7.  JESD204B IP Core Parameter Configuration

Parameter

Value

Description

Subclass

1

Subclass mode.

L

4

Number of lanes per converter device.

M

2

Number of converters per device.

F

1

Number of octets per frame.

S

1

Number of transmitted samples per converter per frame.

N

14

Number of conversion bits per converter.

N’

16

Number of transmitted bits per sample.

K

32

Number of frames per multiframe.

CS

0

Number of control bits per conversion sample.

CF

0

Number of control words per frame clock period per link.

HD

0

High Density user data format.

SCR

Off

Enable scramble.

The JESD204B IP base core connects to the ARM HPS via the Avalon-MM bridge. There are two separate Avalon-MM ports for the JESD204B IP core:

  • Base core TX data path—for dynamic reconfiguration of the TX CSR parameters.
  • Base core RX data path—for dynamic reconfiguration of the RX CSR parameters.

The ARM® HPS writes to the JESD204B IP core CSR during a dynamic reconfiguration operation. The software instructions to execute dynamic reconfiguration of the JESD204B IP core are described in the User Commands section.

To customize the JESD204B IP core parameters to meet your specifications, follow the instructions in the Modifying JESD204B IP Core Parameters section.

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