AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

The Altera® JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to or from the FPGA devices.

The JESD204B IP core is part of the IP Catalog library, which is distributed with the software and downloadable from the Altera® website.

This reference design demonstrates the JESD204B IP core operating as part of a system that includes:

  • Altera JESD204B transport layer (assembler and deassembler)
  • test pattern generator and checker
  • core PLL
  • Serial Parallel Interface (SPI) – Master module
  • reset sequencer
  • various dynamic reconfiguration controllers
  • ARM® hard processor subsystem (HPS) as the control unit

The key feature of this reference design is the software-based control flow that utilizes the ARM® HPS control unit.

The reference design utilizes the Arria V SoC Development Kit to interoperate with the Analog Devices (ADI) AD9680 ADC daughter card that connects to the development board.

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