AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.8.2. Modifying the Data Rate or Reference Clock Frequency

When changing the data rate or reference clock frequency, be aware of the relationships between the serial data rate, link clock, and frame clock as described in the Core PLL section. Change the PLL output clock settings accordingly to meet the clock frequency requirements. Also note the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters for cases when F=1 or F=2. These parameters further divide down the frame clock frequency requirement so the resulting clock frequency is within bounds of timing closure for the FPGA core fabric. See the Core PLL section for more details on clocking requirements and the System Parameter section for more details on the frame clock division factor parameters. Follow the steps below when changing the serial data rate or reference clock frequency.

  1. Go through the steps in the Modifying JESD204B IP Core Parameters section to open the jesd204b_system.qsys project in the QSYS window.
  2. Double-click the jesd204b module to bring up the JESD204B IP core parameter editor.
  3. Change the Data rate and PLL/CDR Reference Clock Frequency values as necessary to meet your system requirements.
  4. If the clock frequency values for device_clk, link_clk, frame_clk, or mgmt_clk needs to be updated, double-click the relevant clock source module in the jesd204b_system.qsys System Contents tab and modify the clock frequency values accordingly.
  5. Navigate back to the top level jesd204b_ed_soc.qsys hierarchy.
  6. If the clock frequency values for device_clk, link_clk, frame_clk, or mgmt_clk needs to be updated, double-click the relevant clock source module in the jesd204b_ed_soc.qsys System Contents tab and modify the clock frequency value accordingly.
  7. Click Generate HDL to generate the HDL files needed for Quartus compilation.
  8. After the HDL generation completes, click Finish to save your settings and exit the Qsys window.
  9. Change the core PLL reference clock or output clock frequency values, if relevant, to match your system requirements. In the Quartus Project Navigator panel, select IP Components from the pull-down menu and double-click the core_pll entity. This brings up the Altera PLL parameter editor.
  10. In the Altera PLL parameter editor, modify the Reference Clock Frequency value under the General tab to meet your system requirements. Ensure that the reference clock frequency value matches the ones set for the jesd204b module in the Qsys project. Also, change the outclk0 group settings (which correspond to the link clock) and outclk1 group settings (which correspond to the frame clock) if necessary. Ensure that the link clock and frame clock values satisfy the frequency requirements as described in the Core PLL section.
  11. When you are done with the edits, click Finish to save your settings.
  12. If the frame clock settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values need to be changed, modify the relevant system parameters in the top level HDL file, jesd204b_ed.sv as described in the Modifying JESD204B IP Core Parameters section.
  13. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and Programming the Board section.

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