AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.7. Reference Design Software

The key feature of the reference design with ARM® HPS control unit is the ability to control certain aspects of the JESD204B system using a C-based, software control flow. Some of the capabilities enabled by the software control flow are:

  • System reset—ability to reset individual modules (for example, core PLL, transceiver PHY, JESD204B base Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.
  • Initial and dynamic, real-time configuration of external converter devices via SPI interface.
  • Dynamic reconfiguration of key modules in the reference design subsystem (for example, JESD204B IP core base layer, transceiver PHY, core PLL, and so forth).
  • Error handling via interrupt service routines (ISR).
  • Status register read back.
  • Dynamic switching between real-time operation and test mode.

The software C code included as part of the reference design performs basic JESD204B link initialization and brings up the user command prompt, where you can enter commands to perform a wide variety of tasks. Modify the code as necessary to meet your system specifications.

Figure 6. Main C Code Execution Flow

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