AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.4. Reference Design Files

The reference design files are included in a ZIP file (jesd204b_av_soc_ref_design.zip). The ZIP file contains two key components:

  • Quartus project archive file (jesd204b_ed.qar)
  • Software project archive file (jesd204b_soc_baremetal_gnu.tar.gz)
Table 10.  Key Files and Folders in the Quartus Project Archive File

File Type

File/Folder

Description

Quartus project files

jesd204b_ed.qpf

Quartus project file.

jesd204b_ed.qsf

Quartus settings file.

output_files

Folder containing output files from Quartus compilation (for example, reports or .sof).

Verilog HDL design files

jesd204b_ed.sv

Top level HDL

jesd204b_ed.sdc

Synopsys Design Constraints (SDC) file containing all timing or placement constraints.

ip Folder containing Verilog HDL and source files of sub-modules instantiated in top level HDL file.
ip/altera_pll Folder containing Verilog HDL and source files of core PLL module.
ip/altiobuf Folder containing Verilog HDL and source files of output buffer module.
ip/spi_mosi_oe Folder containing Verilog HDL and source files of output buffer module.
ip/debounce Folder containing Verilog HDL and source files of switch debouncer module.
ip/issp Folder containing Verilog HDL and source files of ISSP module.
ip/edge_detect Folder containing Verilog HDL and source files of edge detector module.
ip/transport_layer

Folder containing assembler and deassembler HDL.

ip/pattern

Folder containing the test pattern generator and checker HDL.

Qsys Projects

jesd204b_ed_soc.qsys

Top level Qsys system project.

jesd204b_system.qsys

JESD204B subsystem

After you have imported the software project archive file (jesd204b_soc_baremetal_gnu.tar.gz) into the SoC EDS ARM DS-5 tool (refer to Setting up the Software Command Line Environment section), verify that the software project contains the source and header files as shown in the table below.

Table 11.  Source and Header Files in Software Project

File Type

File

Description

Makefiles

Makefile

Software project compilation Makefile. The ARM DS-5 tool executes this Makefile during build project operation. Whenever you add or remove any *.c source files to or from the project, you must manually update the source file list in this Makefile accordingly. See the Setting up the Software Command Line Environment section for more details.

Header files

system.h

Contains base address definitions of the following Avalon-MM peripherals implemented in the FPGA core fabric:

  • Avalon-MM bridge
  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • Reset sequencer
  • FPGA core control PIO
  • FPGA core status PIO
  • SPI master module

The base addresses correspond to the address maps of the jesd204b_ed_soc.qsys and jesd204b_system.qsys projects in Qsys. Whenever you make any changes to the address maps in Qsys, you must manually update the base addresses in this file accordingly.

altera_jesd204_regs.h

Contains offsets, masks, and bit position definitions for peripherals in the QSYS system that do not have standard access libraries. This includes the following peripherals:

  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • Reset sequencer
  • FPGA core control PIO
  • FPGA core status PIO

main.h

General user parameter definitions. See Software Parameters section for detailed description of the user parameters.

functions.h

Contains function prototype definitions of sub-functions in main.c.

rules.h

Contains function prototype definitions of rule functions in rules.c.

macros.h

Contains function prototype definitions of macro functions in macros.c.

Source files

main.c

Main C program. Also contain sub functions.

rules.c

Rule checking functions used by the dynamic reconfiguration functions.

macros.c

JESD204B Qsys system device access macros.

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