AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.3.4. Test Pattern Generator

The test pattern generator generates one of three patterns—parallel PRBS, alternate checkerboard, or ramp wave—and sends the pattern along to the transport layer during test mode. The test pattern generator has many customization options and you can modify the test pattern generator HDL code to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. The software instructions to execute dynamic reconfiguration of the test pattern generator are described in the User Commands section.

Note: The test pattern generator is implemented in the top level HDL file, not in the Qsys project.

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