AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Document Table of Contents JESD204B Subsystem

The JESD204B subsystem Qsys project (jesd204b_system.qsys) instantiates these modules:

  • JESD204B IP core configured in duplex (with TX and RX data paths), non-bonded mode
  • Reset sequencer
  • Transceiver PHY reset controller
  • Avalon-MM bridge

The grouping of modules into a single Qsys subsystem project facilitates easy implementation of multi-link capabilities. For every link that you implement, a jesd204b_system.qsys project is instantiated in the top level Qsys project and assigned an address as described in the Top Level Address Map section. You can reset and dynamically reconfigure each link independently.

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