AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Document Table of Contents Reset Sequencer

The reset sequencer is a standard Qsys component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:

  • Core PLL reset—resets the core PLL.
  • Transceiver reset—resets the JESD204B IP core PHY module.
  • TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs.
  • TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer.
  • TX/RX frame reset—resets the TX/RX transport layer, downstream modules.

The reset sequencer has hard and soft reset options. The hard reset port connects to the ARM® HPS-generated FPGA reset output signal (h2f_reset). The ARM® HPS executes a soft reset by issuing the reset command to the Avalon-MM interface of the reset sequencer. When you assert a hard reset or issue the full sequence reset command, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

Figure 5. Reset Sequence

Did you find the information on this page useful?

Characters remaining:

Feedback Message