AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.7.5.1. Functions in main.c Source File

The function prototypes of the functions listed in the table below can be found in the functions.h header file.

Table 17.  Functions in main.c
Function Prototype Description
void chomp (char * string) Chomps trailing '\n' character from string.
int StringIsNumeric (char * string) Tests whether string is numeric.

Returns 1 if true, 0 if false.

int StringIsHex (char * string) Tests whether string is a hexadecimal number.

Returns 1 if true, 0 if false.

void DelayCounter (alt_u32 count) Delay counter. Counts up to count ticks, each tick is roughly 1 second (not accurate).
void Get_L_Init (int * L_init) Read initially configured value of L from each JESD204B IP core CSR in the design and store the value in L_init array.
void Get_F_Init (int * F_init) Read initially configured value of F from each JESD204B IP core CSR in the design and store the value in F_init array.
void Get_FC_Init (int * FC_init , int * DR_init) Calculate initially configured value of the frame rate by reading the relevant parameters from each JESD204B IP core CSR in the design and the serial data rate values stored in DR_init. Stores calculated value in FC_init array.
int Initialize (char * options [][], int * held_resets) Executes initialize command according to options. This function performs the following actions:
  • Set link to test mode (source or destination set to PRBS test pattern generator or checker, transceiver set to serial loopback mode) or negate
  • Pulse sysref
  • Wait 10 seconds
  • Report link status
Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if pattern checker errors found, 6 if both sync errors and pattern checker errors found.
void Help (void) Prints menu of available commands.
int Reset (char * options [][], int * held_resets) Executes reset command according to options. This function calls two other subfunctions depending on options:
  • Reset sequence (initiate full hardware reset sequence)
  • Reset force (force individual resets high, low, or pulse depending on options)
Returns 0 if success, 1 if fail.
int LoadSPI (char * options [][]) Executes the load SPI command according to options.

Returns 0 if success, 1 if fail.

int GetSPI (char * options [][]) Executes get SPI command according to options.

Returns 0 if success, 1 if fail.

int ConfigSPI (int * held_resets , int dnr) Executes the configure SPI command according to options.

Returns 0 if success, 1 if fail.

int Status (char * options [][]) Executes the report link status command according to options.

Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if pattern checker errors found, 6 if both sync errors and pattern checker errors found.

int Loopback (char * options [][], int * held_resets , int dnr) Executes the loopback command according to options.

Returns 0 if success, 1 if fail.

int SourceDest (char * options [][], int * held_resets , int dnr) Executes the source or destination datapath selection command according to options.

Returns 0 if success, 1 if fail.

int Test (char * options [][], int * held_resets) Executes the test mode command according to options. Test mode:
  • Set source or destination datapath selection to PRBS test pattern generator or checker.
  • Set transceiver to serial loopback mode.
Returns 0 if success, 1 if fail.
int Reinit (char * options [][], int * held_resets) Executes the reinit command according to options. This function performs the following actions:
  • Write reinit values to the appropriate registers in the JESD204B IP core CSR to trigger reinit operation
  • Pulse sysref
  • Wait 10 seconds
  • Report link status
Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if pattern checker errors found, 6 if both sync errors and pattern checker errors found.
void Sysref (void) Pulse SYSREF signal one time (that is in "one-shot").
int Reconfig (char * options [][], int * L_init , int * F_init , int * DR_init , int * FC_init , int * current_dr_div , unsigned int link_clk_pll_ counter_val_init , unsigned int frame_clk_pll_ counter_val_init , unsigned int * xcvr_native_ array_ptr [][], unsigned int * xcvr_pll_ array_ptr [][], int * held_resets) Executes dynamic reconfiguration command. This function performs three major tasks:
  • Parses user options to identify the parameters and values to be dynamically reconfigured by user
  • Performs rule-checking to ensure all values entered conform to valid ranges
  • Performs read-modify-writes (RMW) to relevant CSR registers based on valid options entered by user
There are four categories of the CSR register RMWs performed by the software:
  • Write new parameter values to the TX/RX JESD204B CSR ilas_data1 and ilas_data2 registers.
  • Write to TX/RX JESD204B CSR lane_control_n registers to power-down or power-up lanes in response to changes in L parameter.
    Note: This feature is not fully implemented in the hardware.
  • Write to the core PLL reconfiguration module in response to changes in link or frame clock data rate.
  • Write to the transceiver reconfiguration interface and/or ATX PLL reconfiguration interface in response to changes in transceiver serial data rate.
For more details on dynamic reconfiguration features, refer to the Dynamic Reconfiguration section.

Returns 0 if success, 1 if fail.

void ResetHard (void) Triggers full hardware reset sequence via PIO control registers.
int ResetSeq (int link , int * held) Performs full hardware reset sequence on the indicated link via software interface .

Returns 0 if success, 1 if fail.

int ResetForce (int link , int reset_val , int hold_release , int * held_resets) Forces reset assertion or deassertion on submodule resets for the link indicated by reset_val. The function also decides whether to assert and hold (hold_release =2), deassert ( hold_release =1) or pulse ( hold_release =0) indicated resets. The function has mechanisms (using the global held_resets flag) to ensure that held resets that are not the target of the reset force function are not affected by it.

Returns 0 if success, 1 if fail.

int Reset_PLL_Release (int link, int * held_resets) Deassert the core PLL reset signal. Wait until the core PLL locked signal assert before returning.

Returns 0 if success, 1 if fail.

int Reset_X_L_F_Release (int link, int * held_resets) Deassert the transceiver, link, and frame resets. This function deasserts the TX transceiver reset first, waits until the TX transceiver ready signal asserts, then deasserts the TX link and TX frame resets. The function then repeats the above actions with the RX data path.

Returns 0 if success, 1 if fail.

void spiWrite (alt_u16 offset, alt_u8 m_data, alt_u8 slave) Performs SPI write operation of m_data to SPI slave indicated by slave number at address offset offset. The maximum bit width of m_data is 8 bits while the maximum bit width of offset is 16 bits.
alt_u8 spiRead (alt_u16 offset, alt_u8 slave) Performs SPI read operation of SPI slave indicated by slave number at address offset offset. Returns 8-bit read value. The maximum bit width of offset is 16 bits.
void spiVerify (alt_u16 offset , alt_u8 slave, alt_u8 data) Performs SPI read operation of SPI slave indicated by slave number at address offset offset, compares the read data to data, then reports whether the read data matches the user-given data. The maximum bit width of data is 8 bits while the maximum bit width of offset is 16 bits.
void Config_AD9680 (alt_u8 slave) Executes a series of spiWrites to the AD9680 slave to configure it.
void InitISR (void) Initialize the interrupt controllers for the following peripherals:
  • JESD204B IP core TX CSR
  • JESD204B IP core RX CSR
  • SPI master
The timer and JTAG UART interrupt controllers are disabled. Modify the function to enable it.
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