AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.3.1.2.1. ARM HPS Control Unit

The ARM® HPS is configured with the following input resets enabled:

  • Cold reset
  • Warm reset
  • Debug reset

The reset pulses to the ARM® HPS are generated by the Altera In-System Sources and Probes (ISSP) module that is instantiated in the top level HDL file. The reset pulses are shaped by the edge detector unit (also instantiated in the top level HDL file) to meet the ARM® HPS reset pulse specifications. The ARM® HPS in turn generates an output reset signal to the FPGA core fabric via the HPS-to-FPGA external reset port (h2f_reset) and is used by the JESD204B subsystem reset sequencer.

The ARM® HPS communicates with the FPGA core fabric via a set of AXI bridges that are part of the HPS:

  • HPS-to-FPGA bridge—64-bit master interface that interfaces to the on-chip memory
  • FPGA-to-HPS bridge—64-bit general purpose slave interface from the FPGA core fabric to ARM® HPS
  • Lightweight HPS-to-FPGA bridge—32-bit master interface that connects to all Avalon-MM peripherals that are implemented in the FPGA core fabric

The SDRAM interface protocol setting is configured to DDR3 operating at 533 MHz.

The following peripherals have their interrupt request (IRQ) output ports connected to the IRQ input port of the ARM® HPS (f2h_irq0):

  • Push button input PIO module
  • DIP switch input PIO module
  • SPI master module
  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • Reset sequencer
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