AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.3.1.2.1. ARM HPS Control Unit

The ARM® HPS is configured with the following input resets enabled:

  • Cold reset
  • Warm reset
  • Debug reset

The reset pulses to the ARM® HPS are generated by the Altera In-System Sources and Probes (ISSP) module that is instantiated in the top level HDL file. The reset pulses are shaped by the edge detector unit (also instantiated in the top level HDL file) to meet the ARM® HPS reset pulse specifications. The ARM® HPS in turn generates an output reset signal to the FPGA core fabric via the HPS-to-FPGA external reset port (h2f_reset) and is used by the JESD204B subsystem reset sequencer.

The ARM® HPS communicates with the FPGA core fabric via a set of AXI bridges that are part of the HPS:

  • HPS-to-FPGA bridge—64-bit master interface that interfaces to the on-chip memory
  • FPGA-to-HPS bridge—64-bit general purpose slave interface from the FPGA core fabric to ARM® HPS
  • Lightweight HPS-to-FPGA bridge—32-bit master interface that connects to all Avalon-MM peripherals that are implemented in the FPGA core fabric

The SDRAM interface protocol setting is configured to DDR3 operating at 533 MHz.

The following peripherals have their interrupt request (IRQ) output ports connected to the IRQ input port of the ARM® HPS (f2h_irq0):

  • Push button input PIO module
  • DIP switch input PIO module
  • SPI master module
  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • Reset sequencer

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