AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Public
Document Table of Contents

1.8.3.2. Editing the Top Level HDL File

  1. Open the top level HDL file (jesd204b_ed.sv) in any text editor of your choice.
  2. Modify the LINK system parameter to reflect the number of links in your design.
  3. Replace the single-link jesd204b_ed_soc instance with the multi-link one generated from Editing the QSYS Project section above.
  4. Reconnect in a similar way all the ports that are similar between the single-link jesd204b_ed_soc instance and the multi-link one.
  5. The ports that are new in the multi-link jesd204b_ed_soc instance are the ports associated with the jesd204b_subsystem_1 module. Connect the ports that have jesd204b_subsystem_1_* prefix as shown in the example below:
    .jesd204b_subsystem_1_jesd204b_txlink_rst_n_reset_n
    (tx_link_rst_n[1]),
    
  6. Repeat step 5 for subsequent links in your design.
  7. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and Programming the Board section.

Ensure that any additional pins that are available from the addition of multi-links (for example, tx_serial_data and rx_serial_data pins) have the proper pin assignments in the Quartus settings file (jesd204b_ed.qsf).

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