AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.1. Reference Design Overview

This reference design is implemented on the Arria V SoC development board interoperating with the ADI AD9680 ADC converter card.

Figure 1. JESD204B Reference Design with ARM HPS Control Unit Block DiagramFigure shows a system level block diagram of the JESD204B system reference design with the ARM® HPS control unit.

The reference design consists of these components and sub components:

  • Qsys system:
    • ARM® HPS control unit and various processor peripherals
    • JESD204B subsystem
    • SPI master module
  • Top level HDL:
    • Core PLL
    • In-system source and probes (ISSP)
    • Edge detectors
    • Altera transport layer (assembler and deassembler)
    • Test pattern generator and checker
  • ARM® HPS control unit—generates a one-shot SYSREF pulse for the JESD204B IP core and the AD9680 module (for Subclass 1 mode compliance).
  • device_clk (153.6 MHz) clock signal sourced from the AD9516 external clock module—acts as the reference clock for the on-chip core PLL and transceiver PHY PLL.
  • Core PLL module—generates the link clock (link_clk) and frame clock (frame_clk).
  • Oscillator on-board the Arria V SoC development board—supplies a 50 MHz clock (fpga_clk_50) to clock the control plane.
  • Altera In-System Source and Probes (ISSP) module instantiated in the top level HDL—generates the following resets for the ARM HPS control unit:
    • Cold reset
    • Warm reset
    • Debug reset
  • Edge detect module instantiated in the top level HDL—shapes the reset pulses generated by the ISSP module to meet the ARM HPS reset pulse width requirements.
  • AD9516 external clock module
    • Supplies a 614.4 MHz clock to the ADCs on the AD9680 module via an SMA connector.
    • Supplies a 153.6 MHz reference clock to the FPGA via an SMA connector on the AD9680 module. The reference clock is passed through from the AD9680 module to the FPGA via the FMC connector.
    • You can replace this module with any external clock module that supplies a 614.4 MHz and 153.6 MHz reference clock.
  • AD9680 module
    • Configuration of the AD9680 converter parameters is through a 4-wire SPI master module via FMC connector.
    • Configured to transmit on 4 high-speed transceiver lanes (L=4) to the FPGA.
    • Each lane is configured to 6.144 Gbps data rate.
    • Passes through the FPGA reference clock (device_clk) from the AD9516 clock module to the FPGA via the FMC connector.
Table 2.  System ClockingThis table summarizes the system clocking of the reference design.

Clocks

Description

Source

Modules Clocked

device_clk

Reference clock for the data path

External

Core PLL, transceiver PHY PLL

link_clk

Link layer clock

device_clk

JESD204B IP core link layer, transport layer link interface

frame_clk

Frame layer clock

device_clk

Transport layer, test pattern generator and checker, downstream modules

fpga_clk_50

Control plane clock

External

ARM HPS control unit and any peripherals connected to ARM HPS via Avalon-MM/AXI bus interconnect

Related Information
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