AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

ID 683776
Date 12/30/2015
Document Table of Contents

1.3.1. Qsys System

The top level Qsys system (jesd204b_ed_soc.qsys) instantiates the following key components:

  • ARM® HPS control unit and supporting processor peripherals
  • JESD204B subsystem
Figure 3. Qsys System Block Diagram

The main data path flows through the JESD204B subsystem. In this reference design, the JESD204B IP core is configured in duplex mode with both TX and RX data paths. On the TX data path, user data flows from the transport layer through the JESD204B IP core base module via a 32-bit per transceiver lane Avalon® Streaming (Avalon-ST) interface and out as serial data to either the external converters or the RX data path in internal serial loopback mode via the JESD204B IP core PHY module. On the RX data path, serial data flows from the external converters (or from the TX data path, in internal serial loopback mode) to the JESD204B IP core PHY module and out from the JESD204B IP core base module to the transport layer via a 32-bit per transceiver lane Avalon-ST interface. Since the system is configured to 4 transceiver lanes (L=4), the total bit width of the Avalon-ST interface for both the TX and RX data paths is 128 bits.

The control path is centered on the ARM® HPS control unit that connects to various peripherals via the Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) bus protocol. Altera processor peripherals primarily use the Avalon® Memory-Mapped (Avalon-MM) protocol for bus connectivity. The Qsys tool automatically and seamlessly translates between the two protocols such that you can connect an Avalon-MM peripheral to the ARM® HPS interface directly. An Avalon-MM bridge module provides a single memory-mapped interface between the ARM® HPS lightweight HPS-to-FPGA bridge AXI interface and Avalon-MM peripherals implemented in the FPGA core fabric.

A secondary control path from the SPI master module links to the SPI configuration interface of the external converters via a 4-wire SPI interconnect. The configuration of the external converters is done by the ARM® HPS control unit writing configuration data to the SPI master module. The SPI master module handles the serial transfer of data to the SPI interface on the converter end via the 4-wire SPI interconnect.

To view the top level Qsys system in Qsys:

  1. Launch the Quartus® Prime software.
  2. On the File menu, click Open.
  3. Browse and select the jesd204b_ed_soc.qsys file located in the project directory.
  4. Click Open to view the Qsys system.

Did you find the information on this page useful?

Characters remaining:

Feedback Message