PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
ID
683716
Date
1/12/2024
Public
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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel Agilex® 7 F-Series and I-Series Devices Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
5.4. I/O Standards
The PHY Lite for Parallel Interfaces Intel® FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.
I/O Standard | Valid Input Terminations (Ω) 15 | Valid Output Calibrated/Uncalibrated Terminations (Ω)15 | RZQ (Ω) 16 | Differential/Complementary I/O Support |
---|---|---|---|---|
SSTL-12 17 | 60, 120 | 40, 60 | 240 | Yes |
SSTL-125 17 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 17 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 17 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I 18 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-15 Class II18 | 0, 50 | 0, 25 | 100 | Yes |
SSTL-18 Class I18 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-18 Class II18 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V HSTL Class I18 | 0, 50 | 0, 50 | 100 | Yes |
1.2-V HSTL Class II18 | 0, 50 | 0, 25 | 100 | Yes |
1.5-V HSTL Class I18 | 0, 50 | 0, 50 | 100 | Yes |
1.5-V HSTL Class II18 | 0, 50 | 0, 25 | 100 | Yes |
1.8-V HSTL Class I18 | 0, 50 | 0, 50 | 100 | Yes |
1.8-V HSTL Class II18 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
I/O Standard | Valid Input Terminations (Ω) 15 | Valid Output Calibrated/Uncalibrated Terminations (Ω)15 | RZQ (Ω) 16 | Differential/Complementary I/O Support |
---|---|---|---|---|
SSTL-12 19 | 60, 120 | 40, 60 | 240 | Yes |
SSTL-125 19 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 19 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 19 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I 20 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-15 Class II20 | 0, 50 | 0, 25 | 100 | Yes |
SSTL-18 Class I20 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-18 Class II20 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V HSTL Class I20 | 0, 50 | 0, 50 | 100 | Yes |
1.2-V HSTL Class II20 | 0, 50 | 0, 25 | 100 | Yes |
1.5-V HSTL Class I20 | 0, 50 | 0, 50 | 100 | Yes |
1.5-V HSTL Class II20 | 0, 50 | 0, 25 | 100 | Yes |
1.8-V HSTL Class I20 | 0, 50 | 0, 50 | 100 | Yes |
1.8-V HSTL Class II20 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
15 0 is equivalent to no termination.
16 RZQ pin is not required for uncalibrated output terminations.
17 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
18 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.
19 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
20 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.