PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
ID
683716
Date
1/12/2024
Public
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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel Agilex® 7 F-Series and I-Series Devices Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
1.2. Features
Features of the PHY Lite for Parallel Interfaces Intel® FPGA IPs:
- Support input, output, and bidirectional data channels.
- Support the DQS gating and ungating circuitry for strobe-based interfaces.
- Support output delays through interpolator.
- Support dynamic on-chip termination (OCT) control.
- Support quarter-rate, half-rate, and full-rate mode of the interface clock conversions.
- Support input, output, and read enable, strobe enable, and OCT enable paths.
- Support single and double data rates (SDR and DDR) at the I/Os.
- Support the PHY clock tree.
- Support dynamically reconfigurable delay chains using the Avalon® memory-mapped interface.
- Support process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
Note: For Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, you can set the non-PVT compensated component of the input delay through Quartus Settings File (.qsf) assignment in the Intel® Quartus® Prime software.