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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel Agilex® 7 F-Series and I-Series Devices Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
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4.4. I/O Standards
The PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 devices allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.
I/O Standard | Valid Input Terminations (Ω) | Valid Output Terminations (Ω) | RZQ (Ω) | Differential/Complementary I/O Support
Important:
PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 devices does not support differential data pins. |
---|---|---|---|---|
SSTL-12 | 60, 120 | 40, 60,240 | 240 | Yes |
SSTL-125 | 40, 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 | 40, 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 | 40, 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I | 50 | 50 | 100 | Yes |
SSTL-15 Class II | 50 | 25 | 100 | Yes |
SSTL-18 Class I | 50 | 50 | 100 | Yes |
SSTL-18 Class II | 50 | 25 | 100 | Yes |
1.2-V HSTL Class I | 50 | 50 | 100 | Yes |
1.2-V HSTL Class II | 50 | 25 | 100 | Yes |
1.5-V HSTL Class I | 50 | 50 | 100 | Yes |
1.5-V HSTL Class II | 50 | 25 | 100 | Yes |
1.8-V HSTL Class I | 50 | 50 | 100 | Yes |
1.8-V HSTL Class II | 50 | 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
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