PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
ID
683716
Date
1/12/2024
Public
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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel Agilex® 7 F-Series and I-Series Devices Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects
There are interconnects between the sub-banks which chain the sub-banks into a row. The following figures show how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in various Intel Agilex® 7 device variants. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package. Each sub-bank is labeled with ID number to facilitate pin placement.
Figure 17. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGF012 and AGF014, Package R24B
Figure 18. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGF012 and AGF014, Package R24B
Figure 19. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGF014, Package R24C
Figure 20. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGF014, Package R24C
Figure 21. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGF022 and AGF027 Devices, Package R25A
Figure 22. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGF022 and AGF027 Devices, Package R25A
Figure 23. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGF022 and AGF027 Devices, Package R31C
Figure 24. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGF022 and AGF027 Devices, Package R31C
Figure 25. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGI022 and AGI027 Devices, Package R29A
Figure 26. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGI022 and AGI027 Devices, Package R29A
Figure 27. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGI027 Devices, Package R29B
Figure 28. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGI027 Devices, Package R29B
Figure 29. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGI022 and AGI027 Devices, Package R31A
Figure 30. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGI022 and AGI027 Devices, Package R31A
Figure 31. Sub-bank Ordering with ID in Top I/O Row in Intel Agilex® 7 AGI022 and AGI027 Devices, Package R31B
Figure 32. Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex® 7 AGI022 and AGI027 Devices, Package R31B
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