PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 1/12/2024
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices 3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices 4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices 5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 7. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for M-Series Devices Top Level Interfaces 2.2.2. Dynamic Reconfiguration 2.2.3. I/O Timing
2.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for M-Series Devices Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.1.1. Clocks x
2.2.1.1.1. Clock Frequency Relationships
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions
2.5. Design Example x
2.5.1. Generating the Design Example 2.5.2. Verifying Simulation Design Examples using Tester IP
2.5.1. Generating the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Dynamic Reconfiguration Design Examples
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generating the Synthesis Design Example 2.5.1.1.2. Generating the Simulation Design Example
2.5.1.2. Dynamic Reconfiguration Design Examples x
2.5.1.2.1. Generating the Synthesis Design Example 2.5.1.2.2. Generating the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects 3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree 3.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel Agilex® 7 F-Series and I-Series Devices Top Level Interfaces 3.2.4. Dynamic Reconfiguration 3.2.5. I/O Timing
3.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel Agilex® 7 F-Series and I-Series Devices Top Level Interfaces x
3.2.3.1. Clocks 3.2.3.2. Output Path 3.2.3.3. Input Path
3.2.3.1. Clocks x
3.2.3.1.1. Clock Frequency Relationships
3.2.4. Dynamic Reconfiguration x
3.2.4.1. Connectivity 3.2.4.2. Reconfiguration Features and Register Addressing 3.2.4.3. Dynamic Reconfiguration Guidelines
3.2.4.2. Reconfiguration Features and Register Addressing x
3.2.4.2.1. Control Registers Addresses 3.2.4.2.2. Control Registers
3.2.4.3. Dynamic Reconfiguration Guidelines x
3.2.4.3.1. Strobe Enable Window Calibration 3.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 3.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset
3.6. Design Example x
3.6.1. Generating the Design Example
3.6.1. Generating the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generating the Synthesis Design Example 3.6.1.1.2. Generating the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Generating the Synthesis Design Example 3.6.1.2.2. Generating the Simulation Design Example
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices Control Registers Addresses 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces Intel® FPGA IP to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generating the Design Example
4.6.1. Generating the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generating the Hardware Design Example 4.6.1.1.2. Generating the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example 5.7. Application Specific Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Address Registers 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generating the Design Example
5.6.1. Generating the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generating the Hardware Design Example 5.6.1.1.2. Generating the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration with Debug Kit 5.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
5.7. Application Specific Design Example x
5.7.1. Implementation using the PHY Lite for Parallel Interfaces Intel® FPGA IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) for Intel Agilex® 7 M-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) for Intel Agilex® 7 F-Series and I-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Stratix® 10 Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

5.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avalon interface returns a set of values from the control registers. The following tables show the definition of the bits for each control register.
Table 96.  Control Register Description
Feature Bit Description
Pin Output Delay [31:13]

Reserved 14

[12:0]

Phase value

Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation.

Note: The pin output delay switches from the CSR register value to the Avalon register value after the first Avalon write. It is only reset to the CSR register value on a reset of the interface.
Pin Input Delay [31:13]

Reserved 14

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register
[11:9] Reserved 14
[8:0]

Delay value

Minimum Setting: 0

Maximum Setting: 511 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13]

Reserved 14

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[11:10] Reserved14
[9:0]

Delay value

Minimum Setting: 0

Maximum Setting: 1023 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Modifying these values must be done on all lanes in a group.
Strobe Enable Phase [31:16] Reserved 14
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[14:13] Reserved14
[12:0]

Bit [12:0]: Phase value

Minimum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Maximum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

Modifying these values must be done on all lanes in a group.
Strobe Enable Delay [31:16] Reserved14
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[14:6] Reserved14
[5:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 63 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.
Read Valid Delay [31:16] Reserved14
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[14:7] Reserved
[6:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 127 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.
Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.
Related Information
14 Reserved bit ranges must be zero
Level Two Title