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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
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6.4.1. Input Buffer Reference Voltage (VREF)
The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE <mode> -to <pin_name>
Note: The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings (including GPIOs).
VREF Mode | Description |
---|---|
EXTERNAL | Use the external VREF. This is the default. |
CALIBRATED | Use internal VREF generated using VREF codes from the Avalon® memory-mapped interface reconfiguration bus. |
VCCIO_45 | Use internal VREF generated using static VREF code. VREF is 45% of VCCIO. |
VCCIO_50 | Use internal VREF generated using static VREF code. VREF is 50% of VCCIO. |
VCCIO_55 | Use internal VREF generated using static VREF code. VREF is 55% of VCCIO. |
VCCIO_65 | Use internal VREF generated using static VREF code. VREF is 65% of VCCIO. |
VCCIO_70 | Use internal VREF generated using static VREF code. VREF is 70% of VCCIO. |
VCCIO_75 | Use internal VREF generated using static VREF code. VREF is 75% of VCCIO. |
Figure 161. VREF