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1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example
2.2. Software Requirements for the TSN for Drive-on-Chip Design Example
2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example
2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example
2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example
2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example
2.7. Configuring the TSN IP
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example
3.2. Modifying the Drive-On-Chip Qsys System
3.3. Adding the TTTech TSN IP to the Qsys system
3.4. Connecting the TSN and Drive-on-Chip Subsystems
3.5. Compiling the Quartus Prime Design and Top-Level Module
3.6. Generating the Preloader
3.7. Generating a .jic file
3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools
3.9. Launching a YOCTO Build
3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example
3.11. Changing MAC Addresses
3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
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1.2. TSN for Drive-on-Chip Design Example General Description
Intel tests this design in a Cyclone V SoC development kit. This hardware provides flexibility to implement different functionalities required for industrial applications. The design shows you can implement drive-on-chip for motor control and TSN to share information and execute commands.
The HPS (Hard Processor System) allows consolidating the system workload as an embedded device, using a Linux kernel to administrate resources, tasks and drive the hardware with high-level programming methods.
The design has two subcomponents: the TTTech TSN IP and the Drive-on-Chip design example. Qsys integrates the design.
Figure 2. TSN Drive-on-Chip Design Block Diagram.
The HPS within the Cyclone V SoC development board is an Arm Cortex A9 MPCore processor. It manages the TSN IP and communicates through the drive-on-chip using the standard AXI (share memory). Also, different bridges communicate with peripherals and exploit other functionalities.
An instance of the Nios II soft processor in the FPGA controls and manages the resources of the drive-on-chip design. The EPCQ flash memory programs the Nios II soft processor. This program is flashed into the memory as a single instruction file called epcq.hex generated in Nios II Eclipse project.
The soft processor performs all motor driving functions and continuously communicates with the HPS using the corresponding AXI and Avalon interfaces.
The HPS retrieves information from the drive-on-chip design such as rotational speed and quadrature current. Using memory mapping addressing, it can access all the information that the drive-on-chip design generates: motor speed, position, KP gain, KI gain, filter DC gain, wave period and offsets, DC-DC parameters. The HPS can publish all these values to the network using the instantiation of the TSN TTTech IP and some high-level communication protocol such as OPC UA PubSub.
The embedded device allows scalability of its features. You can add new components if using the correct hardware drivers and access other development board resources such as parallel IO, memories, JTAG, UART, SPI, Buttons, LEDs.