1.2. TSN for Drive-on-Chip Design Example General Description
The HPS (Hard Processor System) allows consolidating the system workload as an embedded device, using a Linux kernel to administrate resources, tasks and drive the hardware with high-level programming methods.
The design has two subcomponents: the TTTech TSN IP and the Drive-on-Chip design example. Qsys integrates the design.
The HPS within the Cyclone V SoC development board is an Arm Cortex A9 MPCore processor. It manages the TSN IP and communicates through the drive-on-chip using the standard AXI (share memory). Also, different bridges communicate with peripherals and exploit other functionalities.
An instance of the Nios II soft processor in the FPGA controls and manages the resources of the drive-on-chip design. The EPCQ flash memory programs the Nios II soft processor. This program is flashed into the memory as a single instruction file called epcq.hex generated in Nios II Eclipse project.
The soft processor performs all motor driving functions and continuously communicates with the HPS using the corresponding AXI and Avalon interfaces.
The HPS retrieves information from the drive-on-chip design such as rotational speed and quadrature current. Using memory mapping addressing, it can access all the information that the drive-on-chip design generates: motor speed, position, KP gain, KI gain, filter DC gain, wave period and offsets, DC-DC parameters. The HPS can publish all these values to the network using the instantiation of the TSN TTTech IP and some high-level communication protocol such as OPC UA PubSub.
The embedded device allows scalability of its features. You can add new components if using the correct hardware drivers and access other development board resources such as parallel IO, memories, JTAG, UART, SPI, Buttons, LEDs.
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